Ferroelectric capacitor with electrode formed in separate oxidizing conditions

ABSTRACT

A method of fabricating a ferroelectric capacitor comprises the steps of forming an upper electrode on a ferroelectric film formed on a lower electrode by a sputtering process of a conductive oxide film, wherein the sputtering process is conducted by using a metal target under a first, oxidizing condition and a second, less oxidizing condition.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] The present application is based on Japanese priority applicationNo.11-304628 filed on Oct. 26, 1999, the entire contents of which arehereby incorporated by reference.

BACKGROUND OF THE INVENTION

[0002] The present invention generally relates to semiconductor devicesand more particularly to a ferroelectric capacitor, a semiconductordevice having such a ferroelectric capacitor, and a fabrication processthereof.

[0003] Conventionally, EPROMs and flash memory devices are usedextensively as a non-volatile semiconductor memory device that retainsinformation even when electric power is turned off. These EPROMs andflash memory devices have a floating gate electrode and a tunnelinginsulation film cooperating therewith for retaining information.Particularly, a flash memory device has a simple construction in thatonly a single memory cell transistor is included in a single memory cellsimilarly to the case of a DRAM, and is thus suitable for constructing alarge-scale integrated circuit.

[0004] In a flash memory device, in which writing or erasing ofinformation is achieved by way of hot-electron injection or removal toand from the floating gate electrode via the tunneling insulation film,it is necessary to use a high voltage at the time of writing or erasingoperation. Thus, it is inevitable that a large electric field is appliedto the tunneling insulation film, while such a large electric fieldinduces deterioration of the tunneling insulation film and limits thelifetime of the flash memory device. Further, in view of the fact thatwriting of information is achieved by way of injection of hot electrons,it takes a considerable time for writing information in flash memorydevices. While a flash memory device is capable of storing multi-valueinformation by controlling the amount of the electric charges injectedinto the floating gate electrode, such a possibility of multi-valuestorage of information also indicates the necessity of careful controlof the electric charge injection by taking into account the degree ofdeterioration of the tunneling insulation film. Otherwise, erroneousoperation will be caused.

[0005] A ferroelectric random access memory device is a semiconductormemory device having a ferroelectric capacitor that uses a ferroelectricfilm as the capacitor insulation film and stores information in theferroelectric film in the form of spontaneous polarization of theferroelectric film. In a ferroelectric random access memory device,writing or erasing of information is achieved by inverting the directionof the foregoing spontaneous polarization of the ferroelectric capacitorinsulation film. Such an inversion of the polarization is achieved onlyby way of application of electric voltage and injection of electriccurrent is not necessary. Thus, a ferroelectric random access memorydevice provides the advantageous features of very fast speed of writingoperation and small power consumption. Further, in view of the fact thatthe polarization of the ferroelectric capacitor is limited either to apositive direction or a negative direction, there arises no problem ofexcessive erasing as in the case of a flash memory device.

[0006]FIG. 1 shows the construction of a conventional memory cell of aconventional ferroelectric random access memory device.

[0007] Referring to FIG. 1, the memory cell has a so called 2T/2Cconstruction that uses two transfer gate transistors T₁ and T₂ and twoferroelectric capacitors C₁ and C₂ for storing one-bit information. Inthe construction of FIG. 1, the memory cell achieves a complementaryoperation in which information “1” is stored in one of the capacitorsand information “0” is stored in the other capacitor.

[0008] In more detail, the transfer gate transistors T₁ and T₂ areturned on by selecting a word line WL, and the information “1” or “0” iswritten into the capacitor C₁ from a bit line BIT connected to thetransistor T₁. Simultaneously, the complementary information “0”, or “1”is written into the capacitor C₂ from a complementary bit line /BIT.Thereby, the ferroelectric capacitor insulation films of the capacitorsC₁ and C₂ store the written information in the form of spontaneouspolarization.

[0009] In the reading mode operation of the memory cell, the word lineWL is selected again and the transistors T₁ and T₂ are turned on.Further, the voltage difference appearing across the bit lines BIT and/BIT as a result of the respective polarizations of the ferroelectriccapacitors C₁ and C₂ is detected by a sense amplifier S/A.

[0010] Generally, a ferroelectric material having a perovskite crystalstructure such as PZT having a composition (Pb,Zr)TiO₃ or PLZT having acomposition (Pb, Zr) (Ti,La)O₃ is used for the ferroelectric capacitorinsulation film in the capacitors C₁ and C₂. Alternatively, a Bicompound having a layered structure such as SrBi₂Ta₂O₉ designated as SBTor a compound represented as SrBi₂(Ta,Nb)₂O₉ designated as SBTN may beused for the ferroelectric capacitor insulation film.

[0011] When forming such a ferroelectric capacitor, it is generallypracticed to deposit the ferroelectric film by a sol-gel process orsputtering process in the form of amorphous phase. The amorphous filmthus formed is then subjected to a crystallization process by applying ahigh-temperature annealing process for a very short time. Withoutcrystallization, the film does not provide the desired ferroelectricpolarization.

[0012] In such a crystallizing process, there is a tendency that the PZTor PLZT film undergoes oxygen defect formation. Thus, in order to avoidthe oxygen defect formation and to avoid deterioration of theferroelectric property, it is practiced to carry out the crystallizationprocess-in an oxidizing atmosphere. Thereby, in order to avoid theunwanted problem of oxidation of the lower electrode of theferroelectric capacitor, there is a proposal to carry out thecrystallization process first in an inert atmosphere and then in anoxidizing atmosphere.

[0013] After the foregoing crystallization and oxygen compensationprocess, the upper electrode of the ferroelectric capacitor is formed onthe ferroelectric film thus processed. Conventionally, such a formationof the upper electrode has been achieved by sputtering a refractorymetal film such as a Pt film or an Ir film. As the sputtering process ofthe Pt film or Ir film is conducted in a non-oxidizing atmosphere, therehas been a problem that the oxygen defects are formed again in theferroelectric film with the deposition of the upper electrode.

[0014] In relation to the problem of oxygen-defect formation at the timeof deposition of the upper electrode, there has been a proposal to use aconductive oxide film such as an IrO₂ film for the upper electrode ofthe ferroelectric capacitor. By using such a conductive oxide film forthe upper electrode, the problem of oxygen-defect formation in theferroelectric capacitor insulation film at the time of deposition of theupper electrode is successfully avoided by conducting the deposition ofthe upper electrode in an oxidizing atmosphere, and the problem ofincrease of the resistance of the upper electrode caused by theoxidation is also avoided as a result of use of oxide for the electrode.

[0015] Meanwhile, it has been known that the process of forming an IrO₂electrode film tends to induce the problem of abnormal growth of theIrO₂ crystals leading to the formation of giant IrO₂ crystals. Suchgiant IrO₂ crystals act as defect in the IrO₂ electrode and cause adecrease of yield of production of the semiconductor device. Further,electric properties of the ferroelectric capacitor are deteriorated bythe existence of such giant IrO₂ crystals.

SUMMARY OF THE INVENTION

[0016] Accordingly, it is a general object of the present invention toprovide a novel and useful ferroelectric capacitor and a semiconductordevice having such a ferroelectric capacitor wherein the foregoingproblems are eliminated.

[0017] Another and more specific object of the present invention is toprovide a ferroelectric capacitor having an upper electrode formed of aconductive oxide wherein the amount of switching electric charges of aferroelectric film constituting the capacitor insulation film of theferroelectric capacitor is increased.

[0018] Another object of the present invention is to provide asemiconductor device having a ferroelectric capacitor in which theamount of switching electric charges is increased.

[0019] Another object of the present invention is to provide afabrication process of a semiconductor device having a ferroelectriccapacitor wherein abnormal growth of IrO₂ crystals in an IrO₂ upperelectrode is successfully suppressed.

[0020] Another object of the present invention is to provide a method offabricating a ferroelectric capacitor, comprising the steps of:

[0021] forming a lower electrode;

[0022] forming a ferroelectric film on said lower electrode; and

[0023] forming an upper electrode on said ferroelectric film,

[0024] said step of forming said upper electrode comprising a firstreactive sputtering process of a conductive oxide film and a secondreactive sputtering process of said conductive oxide film conductedafter

[0025] said first reactive sputtering process, said first and secondreactive sputtering process being conducted by using a target of a metalelement constituting said conductive oxide film,

[0026] said first reactive sputtering process being conducted under afirst, oxidizing condition such that oxidation of said metal elementtakes place, said second reactive sputtering process being conductedunder a second, less oxidizing condition.

[0027] Another object of the present invention is to provide aferroelectric capacitor, comprising:

[0028] a substrate,

[0029] an active device formed on said substrate,

[0030] an interlayer insulation film provided on said substrate so as tocover said active device; and

[0031] a ferroelectric capacitor provided on said interlayer insulationfilm in electrical connection with said active device,

[0032] said ferroelectric capacitor comprising: a lower electrode formedon said interlayer insulation film, a ferroelectric film containing Pbformed on said lower electrode; and an upper electrode formed on saidferroelectric film, said upper electrode comprising a conductive oxidefilm deposited on said ferroelectric film, said conductive oxide filmcontaining Pb with a generally uniform concentration in a thicknessdirection thereof, said conductive oxide film comprising a lower partand an upper part, said upper part containing more proportion of saidmetal in a metallic state as compared with said lower part.

[0033] According to the present invention, the problem of oxygen defectformation in the ferroelectric film at the time of formation of theupper electrode is successfully eliminated by forming the upperelectrode by conducting a sputtering process of a conductive oxide filmunder an oxidizing condition. By reducing the thickness of theconductive oxide film thus formed, the abnormal growth of giant crystalsin the conductive oxide film is suppressed, and the yield of productionof the semiconductor device is improved substantially. Further, itbecomes possible to deposit the conductive oxide film with an increaseddeposition rate without deteriorating the electric properties of theferroelectric film, by depositing the conductive oxide film first with astrong oxidizing condition, followed by a less strong oxidizingcondition. The conductive oxide film thus formed by such a two-stepprocess that uses the strong oxidizing condition and less strongoxidizing condition contains Pb that constitutes the ferroelectric film,with a generally uniform concentration level in the thickness directionof the conductive oxide film.

[0034] Other objects and further features of the present invention willbecome apparent from the following detailed description when read inconjunction with the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0035]FIG. 1 is a circuit diagram showing the construction of aconventional ferroelectric random access memory device;

[0036]FIG. 2 is a cross-sectional diagram showing the construction of aferroelectric capacitor according to a first embodiment of the presentinvention;

[0037]FIG. 3 is a diagram showing the relationship between thereflectance of an IrO₂ film formed by a reactive sputtering process anda gas flow-rate in relation to the first embodiment of the presentinvention;

[0038]FIG. 4 is a diagram showing the relationship between thereflectance of an IrO₂ film formed by a reactive sputtering process anda sputtering power in relation to the first embodiment of the presentinvention;

[0039]FIG. 5 is a diagram showing the relationship between the switchingelectric charge of the ferroelectric capacitor of FIG. 2 and asputtering power;

[0040]FIG. 6 is a diagram showing an example of defects formed in anIrO₂ film deposited according to a conventional process;

[0041]FIGS. 7A and 7B are diagrams showing further examples of thedefects formed in an IrO₂ film deposited according to a conventionalprocess;

[0042]FIG. 8 is a diagram showing the surface state of an IrO₂ filmformed according to the process of the present invention;

[0043]FIG. 9 is a diagram showing the relationship between thedeposition rate of the IrO₂ film formed according to the process of thepresent invention and a sputtering power;

[0044]FIG. 10 is a diagram showing the electric property of theferroelectric capacitor formed according to the process of the presentinvention;

[0045]FIG. 11 is a diagram showing the X-ray diffraction pattern of anIrO₂ film formed with a sputtering power of 1 kW;

[0046]FIG. 12 is a diagram showing the X-ray diffraction pattern of anIrO₂ film formed with a sputtering power of 2 kW;

[0047]FIG. 13 is a diagram showing the X-ray diffraction pattern of anIrO₂ film formed by a two-step process that uses a sputtering power of 1kW at the beginning and then increasing to 2 kW;

[0048] FIGS. 14A-14E are diagrams showing the SIMS profile of variouselements in an IrO₂ film formed under various sputtering conditions; and

[0049] FIGS. 15A-15R are diagrams showing the fabrication process of aferroelectric random access memory according to a second embodiment ofthe present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0050] [First Embodiment]

[0051]FIG. 2 shows the construction of a ferroelectric capacitoraccording to a first embodiment of the present invention.

[0052] Referring to FIG. 2, a Si substrate 11 carries thereon a CMOSstructure, and a CVD oxide film 12 is formed on the Si substrate 11 soas to bury the CMOS structure underneath. On the CVD oxide film 12, a Tiadhesion layer 13 is deposited by a sputtering process with a thicknessof about 20 nm, and a lower electrode 14 of Pt is formed on the Tiadhesion layer 13 also by a sputtering process with a thickness of about175 nm. TABLE I below summarizes the sputtering condition of the Tiadhesion layer 13 and the lower electrode 14. TABLE I Ar pressure D.C.power time Ti 0.7 Pa 2.6 kW  9 sec Pt 0.7 Pa 1.0 kW 96 sec

[0053] It should be noted that the lower electrode 14 is by no meanslimited to Pt but may be formed of Ir or Ru or a conductive oxidethereof such as RuO₂ or SrRuO₃.

[0054] On the lower electrode 14, a ferroelectric capacitor insulationfilm 15 of PZT or PLZT is formed by an R.F. sputtering process with athickness of about 200 nm under a condition summarized in TABLE IIbelow. TABLE II Ar pressure R.F. power time PLZT (200 nm) 1.1 Pa 1.0 kW434 sec

[0055] The capacitor insulation film 15 thus formed is then subjected toa crystallization process by applying a rapid thermal annealing (RTA)process at 600° C. for a 60 seconds in an Ar atmosphere containing O₂with a concentration less than about 5%, followed by an oxygencompensating process conducted at 750° C. for 60 seconds forcompensation of any oxygen defects.

[0056] After the formation of the ferroelectric capacitor insulationfilm 15, an upper electrode 16 of IrO₂ is formed on the capacitorinsulation film 15 under the condition summarized in TABLE III below.TABLE III IrO₂ (single step process) pressure  0.8 Pa oxygen flow-rate100 sccm Ar flow-rate 100 sccm power and time  1 kw, 79 secondssubstrate temperature room temperature thickness 200 nm

[0057] Hereinafter, a preliminary explanation of the present embodimentwill be given with reference to FIGS. 3 and 4, wherein FIG. 3 shows theoptical reflectance of the IrO₂ electrode layer 16 thus formed under thecondition of TABLE 3 while changing the oxygen flow-rate and the Arflow-rate variously.

[0058] Referring to FIG. 3, it can be seen that the reflectance of theIrO₂ electrode layer 16 decreases with increased proportion of oxygen inthe sputtering atmosphere, indicating that the proportion of IrO₂ in thelayer 16 increases as a result of progress of oxidation of Ir. In otherwords, the relationship of FIG. 3 indicates that the reflectance of theIrO₂ electrode layer 16 can be used as the index of degree of oxidationof the IrO₂ electrode layer 16.

[0059]FIG. 4, on the other hand, shows the optical reflectance of theIrO₂ electrode layer 16 for the case in which the sputtering power ischanged variously while maintaining the same sputtering atmosphere.

[0060] Referring to FIG. 4, it can be seen that the optical reflectanceincreases with increasing sputtering power, indicating that there occursa reduction in the electrode layer 16 when the sputtering power isincreased and that the electrode layer 16 is primarily formed of metalIr. When the sputtering power is set low, on the other hand, thereoccurs an oxidation in the IrO₂ electrode layer 16 during the sputteringprocess thereof.

[0061] The result of FIGS. 3 and 4 indicates clearly that it ispreferable to use a low sputter power and associated oxidizingatmosphere when forming the upper electrode 16 by IrO₂.

[0062]FIG. 5 shows the relationship between the switching electriccharge Q_(sw) of the ferroelectric capacitor thus formed and thesputtering power used for forming the IrO₂ upper electrode 16.

[0063] Referring to FIG. 5, it can be seen that a large switchingelectric charge Q_(sw) is obtained for the ferroelectric film 15underneath the electrode layer 16 when the sputtering power used forforming the IrO₂ electrode layer 16 is set low. This phenomenonindicates that the sputtering atmosphere has changed to become moreoxidizing as a result of the use of the low sputtering power and theoxidizing atmosphere thus realized has suppressed the reduction of theferroelectric film 15.

[0064]FIG. 6 shows the surface state of the electrode layer 16 observedby electron microscopy for the case in which the electrode layer 16 issputtered consecutively on a number of substrates while setting thesputtering power to 1 kW in accordance with the condition of TABLE III.In FIG. 6, the electrode layer 16 is formed with a thickness of 200 nm.

[0065] According to the experiment, the substrate temperature increasesgradually with the progress of the sputter deposition on the substrates,and because of the gradual rise of the substrate temperature, it wasobserved that giant IrO₂ crystals having a needle shape as representedin FIG. 6 start to appear after the 25th deposition, wherein FIG. 6shows the case in which the sputter deposition was conducted with thesputtering power of 1 kW such that the IrO₂ electrode layer 16 has thethickness of 200 nm.

[0066]FIGS. 7A and 7B show the surface state of the electrode layer 16for the case in which the IrO₂ electrode layer 16 is formed with athickness of 300 nm while setting the sputtering power to 1 kW.

[0067] Referring to FIG. 7A, it can be seen that giant IrO₂ crystals areformed on the electrode layer 16 after the 25th substrate similarly tothe case of FIG. 6, except that the degree of the abnormal crystalgrowth proceeds further to such a degree that development of crystalsurfaces is recognized. As represented in FIG. 7B, such giant IrO₂crystals act as defects on the surface of the electrode layer 16. FromFIG. 7B, it can be seen that the giant IrO₂ crystal appears at theintermediate thickness of the IrO₂ film, suggesting that the abnormalgrowth of the IrO₂ crystal starts when the substrate temperature hasreached a certain temperature as a result of continuation of the sputterdeposition process of the IrO₂ film for some time.

[0068]FIG. 8 shows the surface state of the IrO₂ electrode layer 16 forthe case in which the electrode layer 16 is formed by depositing an IrO₂film by a two-step process, first with a thickness of 100 nm whilesetting the sputtering power to 1 kW, and next for another 100 nm whileincreasing the sputtering power to 2 kW.

[0069] Referring to FIG. 8, the electrode layer 16 has a surface inwhich fine IrO₂ crystals, represented in FIG. 8 by white dots, arescattered uniformly, and the existence of giant crystals as explainedwith reference to FIGS. 7A and 7B is not recognized. In other words,formation of defects in the upper electrode layer 16 is avoided when thedeposition process includes an initial process in which the electrodelayer 16 is formed within the thickness of 100 nm while setting thesputtering power to be 1 kW or less. As long as the initial sputteringprocess is conducted with such a low sputtering power, formation ofdefects in the electrode layer 16 does not occur even when thedeposition of the IrO₂ layer is continued thereon with a differentsputtering condition. It should be noted that FIG. 8 shows the surfacestate of the substrate on which the 100th deposition has been made forthe case in which 100 continuous deposition of the IrO₂ electrode layer16 has been made on 100 substrates.

[0070] Generally, the formation of the giant crystals as represented inFIG. 6 or FIGS. 7A and 7B can be suppressed when the formation of theIrO₂ electrode layer 16 is conducted such that the IrO₂ electrode layer16 has a thickness of 100 nm or less. In the experiments conducted bythe inventor of the present invention, for example, no defect formationwas observed in the 29th or later deposition experiments when the IrO₂electrode layer 16 was formed with the thickness of 100 nm. When theIrO₂ electrode layer 16 was formed with the thickness of 50 nm, nodefect formation was observed in the 30th or later depositionexperiments. Further, the use of the low sputtering power is effectivefor avoiding the reduction of the underlying ferroelectric film 15 andfor realizing excellent electric property for the ferroelectriccapacitor. In the example of FIG. 8, it should be noted that the IrO₂crystals have an average grain size of only 10-30 nm, while in the caseof FIGS. 7A and 7B, the IrO₂ crystals have an average grain size of300-400 nm.

[0071] On the other hand, such a decrease of the sputtering powerinevitably causes a decrease in the growth rate of the electrode layer16 as represented in FIG. 9, wherein it should be noted that FIG. 9represents the relationship between the growth rate of the IrO₂electrode layer 16 and the sputtering power. From FIG. 9, it can be seenthat a growth rate of only 2-3 nm/sec is obtained when the sputteringpower of 1 kW is used.

[0072] Meanwhile, the inventor of the present invention has discoveredthat the switching electric charge Q_(sw) does not change substantiallywhen an IrO₂ electrode layer is formed on the ferroelectric film 15 withlow sputtering power such as 1 kW, followed by the sputtering process ofanother IrO₂ electrode layer designated “A” as represented in FIG. 10with an increased sputtering power or with an increased degree ofreduction in the sputtering atmosphere.

[0073] Referring to FIG. 10, the IrO₂ electrode layer 16 is formed firstby depositing an initial IrO₂ film with a thickness of 100 nm whileusing the sputtering power of 1 kW, followed by depositing a furtherIrO₂ film with a thickness of 100 nm while using the sputtering power of2 kW or 4 kW. The deposition condition of the IrO₂ films thusconstituting the IrO₂ electrode layer 16 is summarized in TABLE IVbelow. TABLE IV IrO₂ (two-step process) pressure  0.8 Pa oxygenflow-rate 100 sccm Ar flow-rate 100 sccm power and time (1^(st) step)  1kW, 29 sec power and time (2^(nd) step)  2 kW, 23 sec substratetemperature room temperature thickness 200 nm

[0074] Thus, the present invention provides an efficient way offabricating a ferroelectric capacitor characterized by an excellentelectric property with improved yield, by first carrying out thedeposition of the IrO₂ electrode layer 16 with a low sputtering power,and then carrying out the deposition with an increased sputtering powerwhile using an oxidizing sputtering atmosphere.

[0075] Further, the inventor of the present invention has discoveredthat the leakage current of 1.50×10⁻⁴ A/cm² for the ferroelectriccapacitor in which the IrO₂ electrode layer 16 is formed with thesputtering power of 2 kW, is reduced to 2.0×10⁻⁵ A/cm² by forming theIrO₂ electrode layer 16 with the sputtering power of 1 kW.

[0076]FIG. 11 shows the X-ray diffraction pattern of the IrO₂ filmobtained by a sputtering process conducted in an atmosphere containingoxygen under the condition of TABLE III while using the sputtering powerof 1 kW.

[0077] Referring to FIG. 11, it can be seen that there is a distinctdiffraction peak corresponding to the (110) surface of IrO₂ at thediffraction angle 2θ of about 28°. Further, a diffraction peakcorresponding to the (200) surface of IrO₂ is observed at thediffraction angle of about 29°.

[0078]FIG. 12, on the other hand, shows the X-ray diffraction pattern ofthe IrO₂ film deposited by a sputtering process conducted under thesputtering power of 2 kW.

[0079] Referring to FIG. 12, the IrO₂ film formed according to such aprocess does not show the reflection of the (110) surface or the (200)surface observed in the case of FIG. 11 but only a strong reflection ofSi is observed.

[0080]FIG. 13 shows the X-ray diffraction pattern of the IrO₂ filmformed according to the condition of TABLE IV explained before.

[0081] Referring to FIG. 13, it can be seen that the IrO₂ film thusformed by the two-step process that uses the low sputtering power at thebeginning and then increasing the sputtering power, shows an X-raydiffraction pattern similar to the one shown in FIG. 11 in that thereare distinct diffraction peaks corresponding to the (110) surface andthe (200) surface of IrO₂.

[0082] FIGS. 14A-14E show the SIMS profile of various elements in theIrO₂ electrode layer 16 thus sputtered under various sputteringconditions, wherein FIG. 14A shows the distribution profile of theelements immediately after the deposition of the IrO₂ electrode layer 16under the condition of TABLE III with the sputtering power of 1 kW,while FIG. 14B shows the distribution profile of the same elements afterapplying a thermal annealing process to the electrode layer 16.

[0083] Referring to FIG. 14A, it can be seen that the Pb concentrationlevel is below the detection threshold in the state immediately afterthe deposition, while FIG. 14B shows that there occurs a substantialdiffusion of Pb from the ferroelectric film 15 into the IrO₂ electrodelayer 16 when the thermal annealing process is applied at 650° C., andthat there is formed a concentration profile of Pb as a result of thethermal annealing process such that the concentration level of Pbdecreases gradually from the interface between the ferroelectric film 15and the IrO₂ electrode layer 16 toward the free surface of the layer 16.

[0084] On the other hand, FIG. 14C shows the distribution profile of theelements in the electrode layer 16 immediately after the state in whichthe electrode layer 16 is formed by a sputtering process conducted withthe sputtering power of 2 kW, while FIG. 14D shows the distributionprofile of the elements for the case a thermal annealing process isapplied to the electrode layer 16 of FIG. 14C.

[0085] Referring to FIG. 14C, it can be seen that the electrode layer 16contains Pb with a concentration level below the detection limit, whilethere appears a distribution profile of Pb in the electrode layer 16after the recovery annealing process as represented in FIG. 14D, suchthat the Pb concentration level is below the detection limit at theintermediate part of the layer 16 while exceeds the detection limit inthe vicinity of the free surface of the layer 16 and the interface tothe ferroelectric film 15.

[0086] Further, FIG. 14E shows the SIMS profile of the elements in theIrO₂ electrode layer 16 for the case the electrode layer 16 is formedunder the condition of TABLE IV while using a low sputtering power of 1kW in the initial period of the sputter deposition process fordepositing the IrO₂ layer to the thickness of 100 nm and increasing thesputtering power to 2 kW after the initial period for depositing theIrO₂ layer for another 100 nm.

[0087] Referring to FIG. 14E, it can be seen that the IrO₂ electrodelayer 16 thus formed contains Pb with a generally uniform concentrationlevel. This profile of Pb is maintained even when a recovery annealingprocess is applied to the ferroelectric film 15.

[0088] It should be noted that the IrO₂ electrode layer 16 of FIG. 14Ethus formed according to the two-step process is in fact formed of alower part contacting with the ferroelectric film 15 and an upper part,wherein the lower part, formed under the strong oxidizing conditioncontains Ir primarily in oxidized state, while the upper part, formedunder less strong oxidizing condition, contains a larger proportion ofIr in the metallic state as compared with the lower part.

[0089] In the present embodiment, it should be noted that the conductiveoxide forming the electrode layer 16 is by no means limited to IrO₂ butother conductive oxides such as RhO₂ or RuO₂, or SrRuO₃ may also beused. Further, it is possible to change the sputtering conditiongradually in the process of TABLE IV for forming the first layer and thesecond layer.

[0090] [Second Embodiment]

[0091] FIGS. 15A-15R show the fabrication process of a semiconductordevice according to a third embodiment of the present invention.

[0092] Referring to FIG. 15A, a p-type well 21A and an n-type well 21Bare formed on a Si substrate 21, which may be any of the p-type orn-type, wherein the Si substrate 21 is covered by a field oxide film 22defining an active region in each of the p-type well 21A and the n-typewell 21B.

[0093] Next, a gate oxide film 33 is formed on the active region of thep-type well 21A and also on the active region of the n-type well 21B,and a p-type polysilicon gate electrode 24A is formed on the gate oxidefilm 23 in the p-type well 21A. Similarly, an n-type polysilicon gateelectrode 24B is formed on the gate oxide film 23 in correspondence tothe n-type well 21B. In the illustrated example, polysiliconinterconnection patterns 24C and 24D are formed further on the fieldoxide film 22 similarly to the polysilicon gate electrodes 24A and 24B.

[0094] In the structure of FIG. 15A, there are formed n-type diffusionregions 21 a and 21 b in the active region of the p-type well 21A byintroducing an n-type impurity element by an ion implantation process,while using the gate electrode 24A and the side wall insulation filmsthereon as a self-alignment mask. Similarly, p-type diffusion regions 21c and 21 d are formed in the active region of the n-type well 21B by anion implantation process of a p-type impurity element, while using thegate electrode 24B and the side wall insulation films thereon as aself-alignment mask.

[0095] The process so far is nothing but an ordinary CMOS process.

[0096] Next, in the step of FIG. 15B, an SiON film 25 is deposited onthe structure of FIG. 15A by a CVD process with a thickness of about 200nm, and an SiO₂ film 26 is further deposited on the SiON film 25 by aCVD process with a thickness of about 1000 nm.

[0097] Further, in the step of FIG. 15C, the SiO₂ film 26 is subjectedto a CMP process while using the SiON film 25 as a polishing stopper,and contact holes 26A-26D are formed in the step of FIG. 15D in the SiO₂film 26 thus planarized such that the diffusion regions 21 a, 21 b, 21 cand 21 d are exposed by the contact holes 26A, 26B, 26C and 26D. In theillustrated example, the SiO₂ film 26 is further formed with a contacthole 26E so as to expose the interconnection pattern 24C.

[0098] Next, in the step of FIG. 15E, a W layer 27 is deposited on thestructure of FIG. 15D so as to fill the contact holes 26A-26E, whereinthe W layer 27 thus deposited is subjected to a CMP process in the stepof FIG. 15F while using the SiO₂ film 26 as a stopper. As a result ofthe polishing process, there are formed W plugs 27A-27E respectively incorrespondence to the contact holes 26A-26E as represented in FIG. 15F.

[0099] Next, in the step of FIG. 15G, an oxidization stopper film 28 ofSiN and an SiO₂ film 29 are deposited consecutively on the structure ofFIG. 15F respectively with the thicknesses of 100 nm and 130 nm,followed by a thermal annealing process conducted in an N₂ atmosphere at650° C. for about 30 minutes. The thermal annealing process is conductedso as to thoroughly remove gases from the structure thus formed.

[0100] Next, in the step of FIG. 15H, a Ti film 30 and a Pt film 31 aredeposited consecutively on the SiO₂ film 29 with respective thicknessesof 20 nm and 175 nm by a sputtering process, which may be conductedaccording to the condition represented in TABLE I. The Ti film 30 andthe Pt film 31 thereon constitute a lower electrode layer of theferroelectric capacitor to be formed.

[0101] After the deposition of the Ti film 30 and the Pt film 31, aferroelectric film 32 of PZT or PLZT is sputter-deposited in the step ofFIG. 15H under the condition of TABLE II, wherein the ferroelectric film32 may contain Ca or Sr.

[0102] Further, in the step of FIG. 15H, the ferroelectric film 32 issubjected to a crystallization process by an RTA process conducted in anoxidizing atmosphere at the temperature of 750° C. for 20 seconds.During the RTA process, any oxygen defects formed in the ferroelectricfilm 32 is compensated for. By using a large rate of temperatureincrease of 125° C./sec, the duration of the thermal annealing processis minimized.

[0103] Further, in the step of FIG. 15H, an IrO₂ film 33 is deposited onthe ferroelectric film 22 thus processed as an upper electrode layerwith a thickness of about 200 nm by a sputtering process conductedaccording to the condition of TABLE IV.

[0104] Next, in the step of FIG. 15I, a resist pattern is formed on theupper electrode layer 23, followed by the patterning of the upperelectrode layer 23 by a dry etching process to form an upper electrodepattern 23A of IrO₂ on the ferroelectric film 32. In the step of FIG.15I, it should further be noted that the ferroelectric film 32 issubjected, after the foregoing sputtering and patterning of the upperelectrode pattern 33A, to a recovery annealing process conducted in anO₂ atmosphere at 650° C. for 60 minutes so as to recover any damagescaused in the ferroelectric film 22 as a result of the foregoingsputtering and patterning processes.

[0105] Next, in the step of FIG. 15J, a resist pattern having a shapecorresponding to the shape of the capacitor insulation film to beformed, is formed on the ferroelectric insulation film 32, and theferroelectric insulation film 32 is subjected to a dry etching processwhile using the foregoing resist pattern as a mask. As a result, adesired ferroelectric capacitor insulation film pattern 32A is formed onthe underlying lower electrode layer 31. Further, an encapsulating layer32B is formed on the lower electrode layer 31 by a ferroelectricmaterial having a composition substantially identical with that of thematerial constituting the ferroelectric film 32, by conducting asputtering process with a thickness of about 20 nm. The encapsulatinglayer 32B thus deposited is then annealed by an RTA process in the O₂atmosphere at 700° C. for 60 seconds with a temperature profile of about125° C./min. The encapsulating layer 32B thereby protects theferroelectric capacitor insulation film pattern 32A from reduction.

[0106] Next, in the step of FIG. 15K, a resist pattern is formed on thelower electrode layer 31 so as to cover the encapsulating layer 32B witha pattern corresponding to the lower electrode pattern to be formed.Further, by conducting a dry etching process on the foregoingencapsulating layer 32B and the underlying Pt and Ti films 30 and 31underneath the encapsulating layer 32B by a dry etching process, a lowerelectrode pattern 31A is formed.

[0107] After the formation of the lower electrode pattern 31A, theresist pattern is removed in the step of FIG. 15K, and the damages thatare introduced into the ferroelectric capacitor insulation film 32Aduring the dry etching process of the lower electrode pattern 31A arerecovered by conducting a recovery annealing process in an O₂ atmosphereat 650° C. for 60 minutes.

[0108] Next, in the step of FIG. 15L, an SiO₂ film 34 is deposited onthe structure of FIG. 15K by a CVD process, typically with a thicknessof about 200 nm, followed by a formation of an SOG film 35 thereon,wherein the SOG film 35 smoothes any sharp steps formed on theunderlying SiO₂ film 34. The SiO₂ film 34 and the SOG film 35 formtogether an interlayer insulation film 36.

[0109] Next, in the step of FIG. 15M, contact holes 36A and 36B areformed in the interlayer insulation film 36 so as to expose the upperelectrode pattern 33A and the lower electrode pattern 31A respectively,and contact holes 36C and 36D are formed further in the step of FIG. 15Nin the interlayer insulation film 36 so as to expose the W plugs 27B and27D respectively through the underlying SiO₂ film 29 and the SiN film28. Further, in the step of FIG. 15M, a recovery annealing process isconducted, after the dry etching process for forming the contact holes36A and 36B, in an O₂ atmosphere at 550° C. for 60 minutes. As a resultof the recovery annealing process, any damages introduced into theferroelectric film patterns 32A and 32B during the dry etching processare eliminated.

[0110] Next, in the step of FIG. 150, a local interconnection pattern37A is formed by a TiN film such that the local interconnection pattern37A connects the contact hole 36A and the contact hole 36C electrically.Further, a similar local interconnection pattern 37B and 37C are formedon the contact holes 36B and 36C.

[0111] Next, in the step of FIG. 15P, an SiO₂ film 38 is formed on thestructure of FIG. 150, and contact holes 38A, 38B and 38C are formed inthe SiO₂ film 38 in the step of FIG. 15Q so as to expose the W plug 27A,the local interconnection pattern 37B and the W plug 27C, respectively.

[0112] Further, in the step of FIG. 15R, electrodes 39A, 39B and 39C areformed respectively in correspondence to the contact holes 38A, 38B and38C.

[0113] Further, the process of forming the interlayer insulation filmand the interconnection patterns may be repeated as desired, to form amultilayer interconnection structure.

[0114] According to the present embodiment, the problem of defectformation in the upper electrode 33A is successfully eliminated whilemaintaining a practical deposition rate when forming the IrO₂ film 33,by conducting the sputtering process in two steps, first with a lowersputtering power and then with an increased sputtering power. Further,such a two-step sputtering process of the IrO₂ layer 33 successfullyprevents deterioration of the electric properties of the ferroelectriccapacitor insulation film 32A.

[0115] Further, the present invention is not limited to the embodimentsdescribed heretofore, but various variations and modifications may bemade without departing from the scope of the present invention.

What is claimed is:
 1. A method of fabricating a ferroelectriccapacitor, comprising the steps of: forming a lower electrode; forming aferroelectric film on said lower electrode; and forming an upperelectrode on said ferroelectric film, said step of forming said upperelectrode comprising a first reactive sputtering process of a conductiveoxide film and a second reactive sputtering process of said conductiveoxide film conducted after said first reactive sputtering process, saidfirst and second reactive sputtering process being conducted by using atarget of a metal element constituting said conductive oxide film, saidfirst reactive sputtering process being conducted under a first,oxidizing condition such that oxidation of said metal element takesplace, said second reactive sputtering process being conducted under asecond, less oxidizing condition.
 2. A method as claimed in claim 1,wherein said first reactive sputtering process is conducted under asputtering power of about 1 kW or less.
 3. A method as claimed in claim1, wherein said second reactive sputtering process is conducted with asputtering power of about 2 kW or more.
 4. A method as claimed in claim1, wherein said first reactive sputtering process and second reactivesputtering process are conducted consecutively while changing asputtering condition continuously from said first condition to saidsecond condition.
 5. A method as claimed in claim 1, wherein said firstreactive sputtering process is conducted such that said conductive oxidefilm is formed with a thickness of about 100 nm or less.
 6. A method asclaimed in claim 1, wherein said conductive oxide film is selected fromthe group consisting of IrO₂, RhO₂, RuO₂ and SrRuO₃.
 7. A ferroelectriccapacitor, comprising: a lower electrode; a ferroelectric filmcontaining Pb formed on said lower electrode; and an upper electrodeprovided on said ferroelectric film, said upper electrode comprising aconductive oxide film of a metal deposited on said ferroelectric film,said conductive oxide film containing Pb with a generally uniformconcentration in a thickness direction thereof, said conductive oxidefilm comprising a lower part and an upper part, said upper partcontaining more proportion of said metal in a metallic state as comparedwith said lower part.
 8. A ferroelectric capacitor as claimed in claim7, wherein said conductive oxide film comprises a compound selected fromthe group consisting of IrO₂, RhO₂, RuO₂ and SrRuO₃.
 9. A ferroelectriccapacitor as claimed in claim 8, wherein said conductive oxide film isformed of crystals of said compound having a generally uniform grainsize, with an average grain size of 10-30 nm.
 10. A ferroelectriccapacitor as claimed in claim 7, wherein said ferroelectric film has aperovskite crystal structure.
 11. A ferroelectric capacitor as claimedin claim 7, wherein said ferroelectric film comprises a zirconatetitanate of Pb.
 12. A semiconductor device, comprising: a substrate, anactive device formed on said substrate, an interlayer insulation filmprovided on said substrate so as to cover said active device; and aferroelectric capacitor provided on said interlayer insulation film inelectrical connection with said active device, said ferroelectriccapacitor comprising: a lower electrode formed on said interlayerinsulation film, a ferroelectric film containing Pb formed on said lowerelectrode; and an upper electrode formed on said ferroelectric film,said upper electrode comprising a conductive oxide film deposited onsaid ferroelectric film, said conductive oxide film containing Pb with agenerally uniform concentration in a thickness direction thereof, saidconductive oxide film comprising a lower part and an upper part, saidupper part containing more proportion of said metal in a metallic stateas compared with said lower part.
 13. A semiconductor device as claimedin claim 12, wherein said conductive oxide film comprises a compoundselected from the group consisting of IrO₂, RhO₂, RuO₂ and SrRuO₃.
 14. Asemiconductor device as claimed in claim 13, wherein said conductiveoxide film is formed of crystals of said compound having a generallyuniform grain size, with an average grain size of 10-30 nm.
 15. Aferroelectric capacitor as claimed in claim 12, wherein saidferroelectric film has a perovskite crystal structure.
 16. Aferroelectric capacitor as claimed in claim 12, wherein saidferroelectric film comprises a zirconate titanate of Pb.
 17. A method offabricating a ferroelectric capacitor, comprising the steps of: forminga lower electrode; forming a ferroelectric film on said lower electrode;and forming an upper electrode on said ferroelectric film, said step offorming said upper electrode comprising a reactive sputtering process ofa conductive oxide film that uses a target of a metal elementconstituting said conductive oxide film, said reactive sputteringprocess being conducted under an oxidizing condition such that oxidationof said metal element takes place, said sputtering process beingconducted while using a sputtering power of about 1 kW or less.
 18. Amethod as claimed in claim 17, wherein said sputtering process isconducted such that said conductive oxide film has a thickness of about100 nm or less.